Generally, various advanced processes may be utilized in design and fabrication of IC devices, particularly to aid with forming components/structures having reduced geometries for higher IC devices. In scaling of fin-type devices, a smaller fin-pitch (FP) may be utilized. However, in smaller technology nodes (e.g., 7 nm or smaller), it is challenging to utilize traditional methods, such as using lithography masks, to form or remove fins. For instance, in forming fins (e.g., fin width of 7 nm) in an SRAM bit-cell, limitations of a lithography process may cause geometrical variations in the fins impacting manufacturing yield and device performance.
Therefore, a need exists for a methodology enabling efficient processes to form and utilize merged spacers in fin generation.